FIG. 1 (Prior Art) is a diagram of a switching power supply 1. This particular power supply is a type of power supply referred to as a “boost” converter or “boost switching power supply”. During a first time period, controller integrated circuit 2 controls switch 3 to be on and conductive such that current flows through the inductor 4 and through the switch 3 and to ground as indicated by arrow 5. As this current flows, energy is stored in inductor 4. Then, in a second time period, controller integrated circuit 2 controls switch 3 to be off and nonconductive. Current in an inductor cannot stop instantaneously, so current flows through inductor 4, through a diode 6, and to a storage capacitor 7 and a load 8. This current flow during the second time period is illustrated in FIG. 2 (Prior Art) by arrow 9. The energy that was stored in inductor 4 is now transferred to capacitor 7 and to load 8. Controller integrated circuit 2 monitors VFB via terminal 10 and rapidly switches switch 3 on and off such that the output current flowing through the load (a string of white LEDs) is regulated to a desired current. The converter is called a “boost converter” because VOUT can be higher than the input supply voltage VIN.
Two performance parameters of the switching power supply are efficiency and noise emissions. Efficiency is equal to output power divided by input power. Power loss within the switching power supply therefore translates into lower power supply efficiency. There are multiple kinds of power loss. One type of power loss is referred to as “transition power loss”, and is equal to the voltage across the switch (VDS) multiplied by the current flow through the switch (IDS). When switch 3 is off, there is no appreciable drain to source current flow through the switch so there is little power loss. When switch 3 is fully on and conductive, there is only a slight drain to source voltage drop across the switch. The switching terminal 11 is very close to ground potential. Accordingly, the product of IDS and VDS is also very small. There is, however, a short period of time when the switch is transitioning. During this transition time there is appreciable drain to source current flow, and there is an appreciable drain to source voltage drop across the switch. Power dissipation during this transition time is therefore also appreciable.
FIG. 3 is a diagram that illustrates the drain to source current IDS and drain to source voltage drop VDS. The dashed line 12 represents the transition power loss. This transition power loss can be reduced by driving the switch harder (with a driver having a lower output impedance) such that switch 3 switches faster. The period of time that IDS and VDS are simultaneously at appreciable levels during a switch transition is therefore reduced, and transition power loss is reduced.
Driving switch 3 harder such that it switches on and off faster, however, results in higher voltage changes (dV/dT) at node SW and undesirable ringing, both of which contribute to EMI (electromagnetic interference) and noise emissions.
FIG. 4 (Prior Art) is a simplified waveform diagram that illustrates operation of the boost converter of FIGS. 1 and 2. When switch 3 turns on, there is ringing as illustrated by reference numeral 13. When switch 3 turns off, there is ringing as illustrated by 14. There are parasitic capacitances on switch node 15. Such parasitic capacitances include a capacitance due to the drain of switch 3, diode 6, a capacitance inherent in inductor 4, and capacitance associated with the physical terminal 11 and interconnect at node 15. This parasitic capacitance of node 15 in combination with the inductance of inductor 4 forms an LC circuit that can ring. The faster switch 3 is turned off and on, the higher the voltage change at SW and the larger the ringing and the larger the resulting radiated noise is seen to be. It is desired simultaneously to increase efficiency and to reduce noise emissions.
FIG. 5 (Prior Art) is a diagram of a first circuit 20 that strives to reduce transition loss without generating excessive noise. Switch 21 is switched on and off to switch current flow through inductor 22 as described above in connection with FIGS. 1 and 2. Input signal SIN on input lead 23 is a pulse train. Inverters 24 and 25 are of increasing drive strength. A second assist path involving inverter 26 and tri-state inverter 27 are provided to increase the drive of the gate of switch 21 during an initial portion of each transition of the signal SIN. FIG. 6 (Prior Art) is a circuit diagram of tri-state inverter 27.
An edge triggered one-shot 29 detects edges of the signal SIN and in response to each such edge generates a pulse. This pulse enabled tri-state inverter 27, thereby allowing the assist path to help in driving the gate of switch 21. Both inverter 25 and tri-state inverter 27 then drive the gate of switch 21. The objective of the circuit is to have this one-shot pulse terminate before the voltage on the gate of switch 21 has completed the voltage transition. When the pulse terminates, tri-state inverter 27 goes high impedance (i.e., “tri-states”) thereby decoupling the assist path from the gate of switch 21. Accordingly, only inverter 25 drives the gate of switch 21 during the remaining portion of the transition. This reduces the rate of change of the voltage on the gate of switch 21 at the end of each transition, and helps to reduce noise and ringing. The rapid rate of change of the voltage on the gate of switch 21 during the initial portion of the transition, however, serves to reduce transition power loss.
The circuit of FIG. 5, however, has many problems. The total duration of the transition of the voltage on the gate of switch 21 is small. Generating a very small pulse for controlling switch 21, where the small pulse has precise timing, may be difficult or impossible to achieve. Making the timing of the pulse track with changing characteristics of switch 21 due to temperature changes, supply voltage changes and/or process changes is difficult to achieve. The circuit is complex and large and therefore expensive to realize in a cost-sensitive switching power supply controller integrated circuit.
FIG. 7 (Prior Art) is a diagram of a second circuit 30 that strives to reduce transition loss without generating excessive noise. In the circuit of FIG. 7, a comparator 31 or other voltage detecting amplifier device compares the voltage on the gate of switch 32 to a reference voltage VREF. Consider a high-to-low voltage transition of the voltage on the gate of switch 32. Initially, the voltage on the gate is higher than VREF. Comparator 31 therefore outputs a digital logic high signal that enables tri-state inverter 33. The assist path involving inverter 34 and tri-state inverter 33 therefore drives the gate of switch 32 along with the primary path involving inverters 35 and 36. The voltage on the gate of switch 32 falls rapidly during this initial time. When the voltage on the gate of switch 32 reaches VREF, comparator 31 switches and disables tri-state inverter 33, thereby disabling the assist path. The desired result is a less rapid change in the voltage on the gate of switch 32 during a final portion of the switching transition. The reduced rate of change of the gate voltage during the final portion of the transition reduces ringing, whereas the rapid change of the voltage on the gate of switch 32 during the initial portion of the transition serves to reduce transition power loss.
The circuit of FIG. 7 has many problems. For example, getting changes in performance of the assist path turn on and turn off circuitry to track changes in operational characteristics of switch 32 may be difficult to achieve. The two types of circuits are different and therefore tend to react to changing conditions differently. Secondly, the comparator and tri-state disable path may not be adequately fast. The voltage on the gate of switch 32 may transition down and reach VREF and continue on downward a substantial amount before comparator 31 detects the crossing of VREF and disables inverter 33 to disable the assist path. Making this assist enable/disable signal path faster may increase power consumption of the comparator an unacceptable amount. Moreover, a comparator such as comparator 31 is a somewhat large circuit and therefore may be expensive to realize in a cost-sensitive switching power supply controller integrated circuit.